As transistor size becomes smaller, more computational components, memories and processing engines can be integrated onto a single chip. This high integration allows for the ability to process more system tasks in parallel to achieve higher system performance.
These computational components, memories and processing engines require a communication fabric for transferring data among them. As the number of processing engines increases, interconnection techniques, such as bus and ring architectures, are no longer scalable to provide enough communication bandwidth for these engines.
On-chip network is an interconnection technique for a large number of processing engines on a single chip. The network includes multiple on-chip routers in which each on-chip router connects to the nearest neighboring on-chip router(s) in the network. Each processing engine is connected to one of the on-chip routers; and, an on-chip router can connect with multiple processing engines. Data communicated among processing engines are transferred through the network of the on-chip routers.
However, there are issues with the on-chip routers of the prior art. For example, the prior art on-chip routers have fixed routing algorithms. As such, the prior art on-chip routers stop working if the addresses of processing engines change or if more processing engines are added or removed from the network. In addition, these prior art on-chip routers only support unicast data packets among processing engines and fixed arbitration schemes.